In a computer system having the main memory in the form of a byte-addressable nonvolatile memory such as a magnetoresistive random access memory (MRAM), a phase-change memory (PCM), or a memristor that is directly connectible to the memory bus of a processor; in order to make sure that, in case there occurs a failure, the operations are continued from the consistent state immediately prior, to the failure, it becomes necessary to ensure that computer programs executed in the processor follow ordering and atomicity (the property that writing is not terminated midway) of the writing performed with respect to the nonvolatile memory.
For example, as a technology for ensuring that the ordering is followed, a technology is known in which the data written by the processor in the nonvolatile memory is divided into groups called epochs that are identified by generation numbers, and control is performed in such a way that the order of write-back from a cache memory to the nonvolatile memory follows the order of epochs.
Moreover, in recent years, memory devices (such as the Hybrid Memory Cube (HMC) or memory devices establishing connection using the QuickPath Interconnect (QPI)) have been developed in which not only the memory has a high operation speed but also a controller is installed for controlling the writing of data in the memory. The target data for writing that is sent from the memory controller of a processor to a memory device firstly goes to the controller in the memory device before being written in the memory.
However, in a memory device having a controller built-in, the following possibility arises: due to a delay occurring in the controller or due to the optimization of the writing order, writing of the data in a nonvolatile memory occurs in a different writing order than the writing order expected by the processor for writing data in a nonvolatile memory. For that reason, it is not possible to ensure that the ordering is followed.